In general, flash memory devices need an output apparatus for selecting a negative voltage for programming, erasing, or reading memory cells.
FIG. 1 illustrates a circuit diagram of an apparatus for selecting a negative voltage for flash memory devices in accordance with the related art.
As shown in FIG. 1, the apparatus for selecting a negative voltage receives a negative voltage signal VN1 and a selection signal SEL for allowing a desired voltage to be outputted to an output terminal OUT. The apparatus includes an inverter INV0, a first high-voltage PMOS transistor PM11, a second high-voltage PMOS transistor PM12, a first high-voltage NMOS transistor NM11, a second high-voltage NMOS transistor NM12, a third high-voltage NMOS transistor NM13, and a fourth high-voltage NMOS transistor NM14.
The inverter INV0 inverts the selection signal SEL to output an inverted selection signal SELb.
The first high-voltage PMOS transistor PM11 has a source and a bulk to which a supply voltage VDD is applied, a gate connected to a node of the inverted selection signal SELb, and a drain connected to a node of a voltage-off signal VEEOFF.
The second high-voltage PMOS transistor PM12 has a source and a bulk to which the supply voltage VDD is applied, a gate to which the selection signal SEL is applied, and a drain to which a voltage-on signal VEEON is applied.
The first high-voltage NMOS transistor NM11 has a source and a bulk to which a negative voltage signal VN1 is applied, a gate to which the voltage-on signal VEEON is applied, and a drain connected to the node of the voltage-off signal VEEOFF.
The second high-voltage NMOS transistor NM12 that has a source and a bulk to which the negative voltage signal VN1 is applied, a gate connected to the node of the voltage-off signal VEEOFF, and a drain connected to the node of the voltage-on signal VEEON.
The third high-voltage NMOS transistor NM13 has a source and a bulk to which the negative voltage signal VN1 is applied, a gate connected to the node of the voltage-on signal VEEON, and a drain connected to an output terminal OUT.
The fourth high-voltage NMOS transistor NM14 has a source to which a ground voltage VSS is applied, a gate connected to the node of the voltage-off signal VEEOFF, and a drain and a bulk connected to the output terminal OUT.
An operation of the apparatus having the above-described configuration is described as follows.
First, when the selection signal SEL is equal to the ground voltage VSS of a logic low, the ground voltage VSS is applied to the gate of the second high-voltage PMOS transistor PM12, and thus, the second high-voltage PMOS transistor PM12 is turned on to output the supply voltage VDD on the node of the voltage-on signal VEEON.
An inverted selection signal SELb has a supply voltage VDD level equal to a logic high, and is produced by the inverter INV0, which inverts the selection signal SEL. The supply voltage VDD, that corresponds to the inverted selection signal SELb, is supplied to the gate of the first high-voltage PMOS transistor PM11, thereby turning off the first high-voltage PMOS transistor PM11.
The supply voltage VDD on the node of the first voltage-on signal VEEON is inputted to the gate of the first high-voltage NMOS transistor NM11 to turn on the first high-voltage NMOS transistor NM11, and thus, the negative voltage signal VN1 is outputted on the node of the voltage-off signal VEEOFF.
The voltage-off signal VEEOFF on the node receiving the negative voltage signal VN1 is applied to the gate of the second high-voltage NMOS transistor NM12 to turn off the second high-voltage NMOS transistor NM12.
The voltage-off signal VEEOFF on the node receiving the negative voltage signal VN1 is applied to the gate of the fourth high-voltage NMOS transistor NM14 to turn off the fourth high-voltage NMOS transistor NM14.
Therefore, when the supply voltage VDD on the node of the voltage-on signal VEEON is inputted to the gate of the third high-voltage NMOS transistor NM13, the third high-voltage NMOS transistor NM13 is turned on, and the negative voltage signal VN1 is outputted on the output terminal OUT.
Next, when the selection signal SEL is equal to the supply voltage VDD of a logic high, the supply voltage VDD is applied to the gate of the second high-voltage PMOS transistor PM12 to turn off the second high-voltage PMOS transistor PM12.
The selection signal SEL is inputted to the inverter INV0, which inverts the selection signal SEL, and thus the node of the inverted selection signal SELb has a ground voltage VSS equal to a logic low.
The ground voltage VSS on the node of the inverted selection signal SELb is inputted to the gate of the first high-voltage PMOS transistor PM11 to turn on the first high-voltage PMOS transistor PM11, and thus, the supply voltage VDD is outputted on the node of the voltage-off VEEOFF.
The supply voltage VDD on the node of the voltage off VEEOFF is inputted to the gate of the second high-voltage NMOS transistor NM12 to turn on the second high-voltage NMOS transistor NM12, and thus, the negative voltage signal VN1 is outputted on the node of the voltage-on VEEON.
The negative voltage signal VN1 on the node of the voltage on VEEON is inputted to the gate of the first high-voltage NMOS transistor NM11 to turn off the first high-voltage NMOS transistor NM11.
The negative voltage signal VN1 on the node of the voltage on VEEON is inputted to the gate of the third high-voltage NMOS transistor NM13 to turn off the third high-voltage NMOS transistor NM13.
Therefore, when the supply voltage VDD on the node of the voltage-off signal VEEOFF is inputted to the gate of the fourth high-voltage NMOS transistor NM14, the fourth high-voltage NMOS transistor NM14 is turned on, and the ground voltage VSS is outputted on the output terminal OUT.
As described above, the apparatus for selecting a negative voltage outputs the negative voltage signal VN1 or the ground voltage VSS on the output terminal OUT according to the logic level of the selection signal SEL.
However, the apparatus for selecting a negative voltage is dedicated for only one negative voltage signal (VN1) and a ground voltage (VSS). Further, in all modes, only when the negative voltage signal is lower than or equal to 0 V corresponding to the ground voltage VSS, is the apparatus for selecting a negative voltage capable of operating.
On the other hand, in flash EEPROMs using a PMOS transistor as a memory element, a plurality of negative voltages may be used depending on modes (e.g., programming, erasure, or read), and a relatively lower voltage among the plurality of negative voltages may be changed depending on modes. For this reason, the related art apparatus for selecting a negative voltage cannot be applied to the flash EEPROMs. For example, when the levels of negative voltages differ depending on a mode such as programming, erasure, or read, the related art apparatus for selecting a negative voltage cannot select and output a desired negative voltage suitable for each mode.